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ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue mar.21.2008 rev. 1.1 revised features & ordering information lead free and green package available to green package available added packing type in ordering information deleted t solder in absolute maximun ratings revised package outline dimension in page 10 revised v ih to 0.7*vcc revised v dr to 1.5v ma y .7.2010 rev. 1.2 revised ordering information in page 11 a ug.25.2010 rev. 1.3 a dded sl grade deleted e grade revised i sb1 /i dr a ug.9.2011 rev. 1.4 revised ?standby power supply current? in page 3 april.30.2012 revised ?data retention current? in page 8
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 55/70ns ? low power consumption: operating current : 30/20ma (typ.) standby current : 4 a (typ.) ll-version 3 a (typ.) sl-version ? single 2.7v ~ 5.5v power supply ? all outputs ttl compatible ? fully static operation ? tri-state output ? data byte control : lb# (dq0 ~ dq7) ub# (dq8 ~ dq15) ? data retention voltage : 1.5v (min.) ? green package available ? package : 44-pin 400 mil tsop-ii 48-ball 6mm x 8mm tfbga general description the ly62w25616 is a 4,194,304-bit low power cmos static random access memory organized as 262,144 words by 16 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly62w25616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. the ly62w25616 operates from a single power supply of 2.7v ~ 5.5v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, typ.) operating(icc,typ.) ly62w25616 0 ~ 70 2.7 ~ 5.5v 55/70ns 4a(ll)/3a(sl) 30/20ma ly62w25616(i) -40 ~ 85 2.7 ~ 5.5v 55/70ns 4a(ll)/3a(sl) 30/20ma functional block diagram control circuit ce# we# oe# decoder 256kx16 memory array column i/o a0-a17 vcc vss dq8-dq15 upper byte dq0-dq7 lower byte i/o data circuit lb# ub# pin description symbol description a0 - a17 address inputs dq0 ? dq15 data inputs/outputs ce# chip enable input we# write enable input oe# output enable input lb# lower byte control ub# upper byte control v cc power supply v ss ground
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? pin configuration tfbga(top view) absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 6.5 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a 0 to 70(c grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity.
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? truth table mode ce# oe# we# lb# ub# i/o operation supply current dq0-dq7 dq8-dq15 standby h x x x x x x h x h high ? z high ? z high ? z high ? z i sb1 output disable l l h h h h l x x l high ? z high ? z high ? z high ? z i cc ,i cc1 read l l l l l l h h h l h l h l l d out high ? z d out high ? z d out d out i cc ,i cc1 write l l l x x x l l l l h l h l l d in high ? z d in high ? z d in d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 2.7 3.0 5.5 v input high voltage v ih *1 0.7*v cc - v cc +0.3 v input low voltage v il *2 - 0.2 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh = -1m a 2.4 2.7 - v output low voltage v ol i ol = 2m a - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il , i i/o = 0ma other pins at v il or v ih - 55 - 30 60 ma - 70 - 20 50 ma i cc1 cycle time = 1 s ce# = 0.2v , i i/o = 0ma other pins at 0.2v or v cc - 0.2v - 4 10 ma standby power supply current i sb1 ce# v R cc - 0.2v others at 0.2v or v cc - 0.2v ll/lli - 4 50 a sl * 5 sli *5 25 - 3 10 a 40 - 3 10 a sl/sli - 3 25 a notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ.) and t a = 25 5. this parameter is measured at v cc = 3.0v
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc -0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh / i ol = -1ma/2m a ac electrical characteristics (1) read cycle parameter sym. ly62w25616-55 ly62w25616-70 unit min. max. min. max. read cycle time t rc 55 - 70 - ns a ddress access time t aa - 55 - 70 ns chip enable access time t ace - 55 - 70 ns output enable access time t oe - 30 - 35 ns chip enable to output in low-z t clz * 10 - 10 - ns output enable to output in low-z t olz * 5 - 5 - ns chip disable to output in high-z t chz * - 20 - 25 ns output disable to output in high-z t ohz * - 20 - 25 ns output hold from address change t oh 10 - 10 - ns lb#, ub# a ccess time t ba - 55 - 70 ns lb#, ub# to high-z output t bhz * - 25 - 30 ns lb#, ub# to low-z output t blz * 10 - 10 - ns (2) write cycle parameter sym. ly62w25616-55 ly62w25616-70 unit min. max. min. max. write cycle time t wc 55 - 70 - ns a ddress valid to end of write t aw 50 - 60 - ns chip enable to end of write t cw 50 - 60 - ns a ddress set-up time t as 0-0- ns write pulse width t wp 45 - 55 - ns write recovery time t wr 0-0- ns data to write time overlap t dw 25 - 30 - ns data hold from end of write time t dh 0-0- ns output active from end of write t ow * 5-5- ns write to output in high-z t whz * - 20 - 25 ns lb#, ub# valid to end of write t bw 45 - 60 - ns *these parameters are guaranteed by device c haracterization, but not production tested.
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout data valid high-z high-z t clz t olz t chz t ohz t oh oe# t oe lb#,ub# t bhz t ace ce# t aa address t rc t ba t blz notes : 1.we#is high for read cycle. 2.device is continuously selected oe# = low, ce# = low, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz.
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow lb#,ub# ce# t aw address t wc t bw write cycle 2 (ce# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw ce# address t wr t as t aw t wc t wp t bw
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? write cycle 3 (lb# ,ub# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw ce# address t wr t as t aw t wc t wp t bw notes : 1.we#,ce#, lb#, ub# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#, lb# or ub# = low. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impe dance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? data retention characteristics parameter symbo l test condition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v 1.5 - 5.5 v data retention current i dr v cc = 1.5v ce# v R cc - 0.2v others at 0.2v or v cc -0.2v ll/lli - 2 30 a sl sli 25 - 2 8 a 40 - 2 8 a sl/sli - 2 23 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) (ce# controlled) vcc ce# v dr R 1.5v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) low vcc data retention waveform (2) (lb#, ub# controlled) vcc lb#,ub# v dr R 1.5v lb#,ub# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.)
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? package outline dimension 44-pin 400mil tsop- package outline dimension symbols dimensions in millmeters dimensions in mils min. nom. max. min. nom. max. a - - 1.20 - - 47.2 a1 0.05 0.10 0. 15 2.0 3.9 5.9 a2 0.95 1.00 1. 05 37.4 39.4 41.3 b 0.30 - 0.45 11.8 - 17.7 c 0.12 - 0.21 4.7 - 8.3 d 18.212 18.415 18.618 717 725 733 e 11.506 11.760 12.014 453 463 473 e1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5 - l 0.40 0.50 0. 60 15.7 19.7 23.6 zd - 0.805 - - 31.7 - y - - 0.076 - - 3 0 o 3 o 6 o 0 o 3 o 6 o
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? 48-ball 6mm 8mm tfbga package outline dimension
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? ordering information
ly62w25616 rev. 1.4 256k x 16 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 12 ? this page is left blank intentionally.

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